• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A screen regulating device and a method for an LCD are provided to convert the frequency and phase of a sampling clock signal used n converting an externally applied analog video signal into a digital signal to sustain an optimum screen condition. CONSTITUTION: The screen regulating device and method for an LCD comprises an A/D converter(110), a graphic controller(120), a data generator(130), a microcomputer(140) and a PLL circuit(100). The PLL circuit(100) converts the frequency of a sampling clock signal in response to an externally applied control signal. The A/D converter(110) converts an analog video signal input from an external computer into a digital signal. The graphic controller(120) scales the converted digital signal to display an image signal on a display panel. The data generator(130) calculates the difference between adjacent two video signals and add the calculated value to generate the first comparison signal. The microcomputer(140) controls overall system.
    公开号:KR20010010482A
    申请号:KR1019990029386
    申请日:1999-07-20
    公开日:2001-02-15
    发明作者:최경오
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    Apparatus and method for automatically controlling screen status of Liquid Crystal Display}
    The present invention relates to a screen state automatic adjustment device of a liquid crystal display device and a method thereof.
    More specifically, the apparatus and method for automatically adjusting the screen state of a liquid crystal display device for maintaining an optimal screen state by converting the frequency and phase of a sampling clock signal used when converting an analog video signal input from an external source into a digital signal. It is about.
    In general, a flat panel display (FPD), such as a liquid crystal display, has a merit of being lightweight and thin, unlike a cathode ray tube monitor, and capable of clearly displaying an image without distortion. Increasingly, the range of applications, including notebook computers, is growing.
    In order to support an analog interface environment for an existing CRT monitor environment, the FPD needs to convert an analog signal into a digital signal and process the same. Therefore, when the analog signal is converted into a digital signal, the clock signal is generated.
    In this case, if the signal source and the above-described generated clock signal phase do not match correctly, the image quality characteristics deteriorate. Therefore, whenever the signal source changes, the phase of the sampling clock signal must be adjusted at any time.
    1 is a block diagram illustrating a configuration of an apparatus for adjusting a screen state of a liquid crystal display device according to the prior art.
    As shown, the PLL circuit unit 100 converts and outputs the phase of the sampling clock signal 101 in response to a control signal input to the microcomputer 140.
    The A / D converter 110 converts an analog video signal input from the computer main body into a digital signal by the sampling clock signal 101 input from the PLL circuit unit 100 described above.
    The graphic controller 120 scales the digital signal converted by the A / D converter 110 described above in response to the control signal input to the microcomputer 140 and displays the image signal on the display panel.
    The microcomputer 140 converts the phase of the sampling clock signal 101 described above in response to a screen adjustment signal input according to a user's key operation, and recognizes the resolution input from the computer main body to control the entire system.
    The microcomputer 140 of the screen state adjusting device of the liquid crystal display device having the above-described configuration recognizes the resolution of the current video mode by a horizontal synchronizing signal input from a computer main body (not shown).
    The control signal for controlling the entire system is output to the A / D converter 110 and the graphic controller 120 by the recognized resolution. The A / D converter 110 then converts the analog video signal input from the computer main body into a digital signal in accordance with the sampling clock signal 101 input from the PLL circuit unit 100 described above.
    The converted digital signal is input to the graphic controller 120, and the graphic controller 120 may display an image signal on the display panel according to the resolution of the current video mode in response to a control signal input from the microcomputer 140. To scale.
    In this case, when the source of the analog video signal input to the A / D converter 110 is changed, the phase of the analog video signal and the sampling clock signal 101 input from the PLL circuit unit 100 to the A / D converter 110 are changed. In this case, the user changes the phase of the above-described sampling clock signal 101 by stepping the screen adjustment key while looking at the display panel, thereby adjusting the image quality.
    However, there is a problem in that the method for adjusting the image quality according to the above-described prior art is inconvenient because the user manually adjusts the image quality by operating a key button for screen adjustment while watching the image signal displayed on the display panel.
    In addition, a general user does not know exactly about the function of adjusting the phase of the sampling clock signal has a problem that can not be properly adjusted.
    Accordingly, an object of the present invention is to provide a liquid crystal display device that maintains an optimal screen state by converting a frequency and a phase of a sampling clock signal used when converting an analog video signal input from an external source into a digital signal so as to solve the above problems. The present invention provides a device for automatically adjusting the screen state and a method thereof.
    1 is a block diagram illustrating a configuration of an apparatus for adjusting a screen state of a liquid crystal display device according to the prior art;
    2 is a block diagram for explaining a configuration of an apparatus for automatically adjusting a screen state of a liquid crystal display device according to the present invention;
    3 and 4 are waveform diagrams for explaining the first embodiment of the present invention,
    5 and 6 are waveform diagrams for explaining a second embodiment of the present invention,
    7 is an operation flowchart for explaining a method for adjusting the screen state of the liquid crystal display device according to the present invention.
    * Description of Signs of Main Parts of Drawings *
    100: PLL circuit part 110: A / D converter
    120: graphic control unit 130: data generation unit
    140: microcomputer
    In the liquid crystal display device according to the present invention for achieving the above object, a first embodiment of the present invention comprises: PLL circuit means for converting and outputting a frequency of a sampling clock signal in response to a control signal input from the outside; A / D converting means for converting an analog video signal input from the computer main body into a digital signal by a sampling clock signal inputted from the circuit means, and a digital signal converted from the A / D converting means in response to a control signal input from the outside. Graphic control means for scaling and displaying an image signal on a display panel, and receiving a video signal from an A / D converting means, calculating a difference between neighboring video signals, and adding the calculated values to generate first comparison data. Reference means for converting the data generating means and the frequency of the sampling clock signal. The first comparison data inputted from the data generating means and the reference data to detect the maximum value, control the sampling clock signal to have the frequency at that time, recognize the resolution input from the computer main body, It includes a microcomputer to control it.
    In addition, a second embodiment of the present invention for achieving the above object is a PLL circuit means for converting and outputting the phase of the sampling clock signal in response to a control signal input from the outside, and a sampling clock signal input from the PLL circuit means; A / D converting means for converting an analog video signal input from the computer main body into a digital signal, and scaling the digital signal converted by the A / D converting means in response to a control signal input from the outside to display an image signal on the display panel. Graphic generating means for displaying, data generating means for detecting the first point and the end point of the horizontal line of the video signal inputted from the A / D converting means, adding the value at that time and outputting the second comparison data, and a sampling clock signal. A reference data for converting the phase of the input signal and input from the data generating means; It includes a microcomputer which compares the comparison data with the reference data to detect the maximum value, controls the sampling clock signal to have the phase at that time, and controls the entire system by recognizing the resolution input from the computer main body.
    Further, the third embodiment of the present invention is characterized in that the PLL circuit means for converting and outputting the phase and frequency of the sampling clock signal in response to the control signal input from the outside, and the sampling clock signal input from the PLL circuit means from the computer main body. A / D converting means for converting an input analog video signal into a digital signal, and graphic control means for displaying an image signal on a display panel by scaling the digital signal converted by the A / D converting means in response to a control signal input from the outside. And receiving the video signal from the A / D converting means, calculating a difference between the neighboring video signals, summing the calculated values to generate first comparison data, and leveling the video signal input from the A / D converting means. Detecting the first point and the end point of the line, adding the values at that time and outputting the second comparison data Data generation means and reference data for converting the frequency and phase of the sampling clock signal, and comparing the first and second comparison data inputted from the data generation means with respective reference data to detect respective maximum values, and sampling It includes a microcomputer that controls the clock signal to have the frequency and phase at that time, and controls the entire system by recognizing the resolution input from the computer main body.
    On the other hand, the method of the present invention for achieving the above object, (1) the process of initializing the memory having a predetermined number of times, (2) receiving the comparison data from the outside, and (3) the comparison data Determining whether the reference data is larger than the set reference data, (4) when the comparison data is larger than the reference data, replacing and storing the reference data with the comparison data, and if the comparison data is smaller, storing the predetermined reference data as it is, (5) In the case of counting the number of times the comparison data is input, (6) determining whether the counted number is equal to the set number of times, and (7) the number of times the counted number is set, the sampling clock signal using the reference data is the same. If the count is less than the set number of times, the process consists of repeating the process from (2).
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    FIG. 2 is a block diagram illustrating a configuration of an apparatus for automatically adjusting a screen state of a liquid crystal display device according to the present invention. The A / D converter 110 and the graphic controller 120 which play the same role as the related art are illustrated in FIG. The description thereof will be omitted, and only the description of the data generator 130, the microcomputer 140, and the PLL circuit unit 100 in which new blocks and functions are enhanced will be described.
    The PLL circuit unit 100 converts the phase or frequency of the sampling clock signal 101 in response to the control signal of the microcomputer 140 and outputs the converted frequency to the A / D converter 110.
    The data generator 130 receives the video signal 111 converted into a digital signal from the A / D converter 110 described above, calculates a difference between two neighboring video signals in a horizontal line, and calculates a result value of the difference. The sum is generated to generate the first data 313.
    On the other hand, the data generation unit 130 receives the video signal 111 converted into a digital signal from the above-described A / D converter 110 detects the first point and the end point of the horizontal line, the value of the detected first point and end point Are summed to generate second data 132.
    The microcomputer 140 compares the first data 131 or the second data 132 input from the data generation unit 130 with the reference data set in the internal memory, and thus the phase of the sampling clock signal 101 described above. Alternatively, the control signal for converting the frequency is output to the PLL circuit unit 100.
    3 and 4 are waveform diagrams for explaining a first embodiment of the present invention. As shown in FIG. 3, FIG. 3 shows a case where the frequency of the sampling clock signal is not optimal. When the difference (Vd0 to Vd3) of each neighboring video signal is calculated and the calculated differences (Vd0 to Vd3) are summed, the case of FIG. 4 is summed in comparison with FIG. 3. The value is not only larger than that of FIG. 3, but also a maximum value.
    Therefore, the microcomputer 140 generates a control signal 141 for converting the frequency of the sampling clock signal 101 output from the PLL circuit unit 100 to detect the maximum value described above, and outputs it to the PLL circuit unit 100. do.
    5 and 6 are waveform diagrams in which the adjustment of the screen state is implemented by converting the phase of the sampling clock signal. As shown in FIG. 5, the phase of the sampling clock signal is not optimal. Indicates the optimum phase of the sampling clock signal. The rising edge of the sampling clock signal 101 is used to detect the first point Vof and the end point Vol of the video signal on the horizontal line of the analog video signal. In the case of summing the values of FIG. 5 and FIG. 6, the summed values of FIG. 6 are not only larger than those of FIG. 5, but also the maximum values.
    Therefore, the microcomputer 140 generates a control signal for converting the phase of the sampling clock signal 101 output from the PLL circuit unit 100 to detect the maximum value described above, and outputs the control signal to the PLL circuit unit 100.
    With reference to the accompanying drawings, the operation of the automatic screen state adjustment apparatus of the liquid crystal display device configured as described above will be described in more detail.
    7 is a block diagram illustrating a method for adjusting a screen state of a liquid crystal display device according to the present invention.
    The first embodiment of the present invention will be described first with reference to FIGS. 2 and 7. First, the microcomputer 140 transmits a control signal to the PLL circuit unit 100 to change the frequency of the sampling clock signal 101. An internal memory (not shown) storing the number of times 141 is initialized (S110).
    In this memory, the number of times set according to the circuit characteristics of the PLL circuit unit 100 is set to an initial value.
    Thereafter, the microcomputer 140 receives the first data 131 from the data generator 130. In operation S130, it is determined whether the first comparison data 131 is larger than the reference data set in the internal memory.
    In this case, when the first comparison data 131 is larger than the reference data, the reference data set in the internal memory is replaced with the first comparison data 131 (S140). In addition, the microcomputer 140 counts (S150) using a counter (not shown) provided therein.
    In operation S160, it is determined whether the number of times set in the internal memory is equal to the number of counts described above.
    As a result of the determination in step S160, when the set number of times and the number of counts are the same, it is determined that the reference data currently stored in the internal memory is the maximum value, and the microcomputer 140 determines that the aforementioned sampling clock signal 101 is the frequency at this time. The control signal 141 is generated to be output to the PLL circuit unit 100 so as to be output.
    At this time, the first comparison data 131 described above is the sum of the difference between two neighboring video signals in the horizontal line of the video signal 111 output from the A / D converter 110 described with reference to FIGS. 3 and 4. to be.
    Meanwhile, in the second exemplary embodiment of the present invention, the second comparison data (131), which is a value obtained by adding the first point and the end point in the horizontal line of the video signal 111 output from the A / D converter 110, 132, and accordingly, the reference data set in the internal memory of the microcomputer 140 is changed, and the sampling clock signal 101 output from the PLL circuit section 100 is executed in the order of FIG. It is intended to find the optimal phase of the sampling clock signal 101 while changing the phase, and the detailed description thereof is similar to that of the first embodiment and will be omitted.
    The third embodiment of the present invention simultaneously accommodates the first comparison data 131 and the second comparison data 132 and changes the frequency and phase of the sampling clock signal 101 output from the PLL circuit unit 100 while changing the sampling clock. Since the signal 101 has an optimal frequency and phase, a detailed description thereof is similar to that of the first embodiment, and will be omitted.
    Therefore, as described above, the present invention detects whenever an analog video signal inputted from a video card of a computer main body to a liquid crystal display device is changed, and the frequency of the sampling clock signal used when converting the analog video signal into a digital video signal. And detecting and setting the optimum frequency and phase while changing the phase, thereby making the image quality of the image signal output to the display panel optimal.
    Of course, there is an effect that the user's convenience is increased by automatically realizing adjusting the image quality state by directly operating the key while watching the display panel.
    While described above with reference to the preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below It will be appreciated.
    权利要求:
    Claims (13)
    [1" claim-type="Currently amended] PLL circuit means for converting and outputting the frequency of the sampling clock signal in response to a control signal input from the outside;
    A / D converting means for converting an analog video signal input from the computer main body into a digital signal by a sampling clock signal inputted from the PLL circuit means;
    Graphic control means for displaying an image signal on a display panel by scaling a digital signal converted by the A / D converting means in response to a control signal input from an external device;
    Data generation means for receiving a video signal from the A / D converting means, calculating a difference between neighboring video signals, and adding the calculated values to generate first comparison data;
    Having reference data for converting the frequency of the sampling clock signal, comparing the first comparison data input from the data generating means with reference data to detect a maximum value, and controlling the sampling clock signal to have a frequency at that time And a microcomputer for controlling the entire system by recognizing the resolution input from the computer main body.
    [2" claim-type="Currently amended] The apparatus of claim 1, wherein the microcomputer compares the first comparison data with the reference data and uses a large value as next reference data.
    [3" claim-type="Currently amended] The apparatus of claim 1, wherein the plurality of control values set in the microcomputer vary according to circuit characteristics of the PLL circuit means.
    [4" claim-type="Currently amended] PLL circuit means for converting and outputting the phase of the sampling clock signal in response to a control signal input from the outside;
    A / D converting means for converting an analog video signal input from the computer main body into a digital signal by a sampling clock signal inputted from the PLL circuit means;
    Graphic control means for displaying an image signal on a display panel by scaling a digital signal converted by the A / D converting means in response to a control signal input from an external device;
    Data generating means for detecting the first point and the end point of the horizontal line of the video signal input from said A / D converting means, adding the value at that time and outputting it as second comparison data;
    Having reference data for converting the phase of the sampling clock signal, comparing the second comparison data input from the data generating means with reference data to detect a maximum value, and controlling the sampling clock signal to have a phase at that time And a microcomputer for controlling the entire system by recognizing the resolution input from the computer main body.
    [5" claim-type="Currently amended] 5. The apparatus of claim 4, wherein the microcomputer compares the second comparison data with the reference data and uses a large value as the next reference data.
    [6" claim-type="Currently amended] 5. The apparatus of claim 4, wherein the plurality of control values set in the microcomputer vary according to the circuit characteristics of the PLL circuit means.
    [7" claim-type="Currently amended] PLL circuit means for converting and outputting the phase and frequency of the sampling clock signal in response to a control signal input from the outside;
    A / D converting means for converting an analog video signal input from the computer main body into a digital signal by a sampling clock signal inputted from the PLL circuit means;
    Graphic control means for displaying an image signal on a display panel by scaling a digital signal converted by the A / D converting means in response to a control signal input from an external device;
    Receives a video signal from the A / D converting means, calculates a difference between neighboring video signals, adds the calculated values, generates first comparison data, and horizontally receives the video signal input from the A / D converting means. Data generating means for detecting the first point and the end point of the line and adding the values at that time and outputting the second comparison data;
    Reference data for converting the frequency and phase of the sampling clock signal, the first and second comparison data input from the data generating means are compared with the respective reference data to detect respective maximum values, and the sampling clock signal And a microcomputer which controls to have a frequency and a phase at that time, and recognizes a resolution input from the computer main body and controls the entire system.
    [8" claim-type="Currently amended] 8. The apparatus of claim 7, wherein the microcomputer compares the first and second comparison data with the respective reference data and uses a large value as the next reference data. .
    [9" claim-type="Currently amended] 8. The apparatus of claim 7, wherein the plurality of control values set in the microcomputer vary according to the circuit characteristics of the PLL circuit means.
    [10" claim-type="Currently amended] (1) initializing a memory having a preset number of times;
    (2) receiving comparison data from an external source;
    (3) determining whether the comparison data is larger than preset reference data;
    (4) if the comparison data is larger than the reference data, replacing and storing the reference data with the comparison data, and if the comparison data is smaller, storing the predetermined reference data as it is;
    (5) counting the number of times of receiving the comparison data;
    (6) determining whether the counted number equals the set number of times;
    (7) If the counted number is the same as the set number of times, the sampling clock signal is controlled using reference data, and if the counted number is less than the set number, the process is repeated from step (2). Method for automatically adjusting the screen state of the liquid crystal display device characterized in that.
    [11" claim-type="Currently amended] The method according to claim 10, wherein the number of times set in the step (6) depends on the characteristics of the means for outputting the sampling clock signal.
    [12" claim-type="Currently amended] The liquid crystal display device according to claim 10, wherein the comparison data of the step (2) is a result of calculating a difference between neighboring video signals among video signals input from the outside and summing the calculated values. How to adjust the screen status automatically.
    [13" claim-type="Currently amended] The screen of the liquid crystal display device according to claim 10, wherein the comparison data of the step (2) is a result obtained by detecting the first point and the end point of the horizontal line of the video signal input from the outside and adding the values at that time. How to adjust status automatically.
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    同族专利:
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    KR100596586B1|2006-07-04|
    JP2001042841A|2001-02-16|
    CN1281154A|2001-01-24|
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1999-07-20|Application filed by 윤종용, 삼성전자 주식회사
    1999-07-20|Priority to KR19990029386A
    2001-02-15|Publication of KR20010010482A
    2006-07-04|Application granted
    2006-07-04|Publication of KR100596586B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR19990029386A|KR100596586B1|1999-07-20|1999-07-20|Apparatus and method for automatically controlling screen status of Liquid Crystal Display|
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